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<title>Memory module</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Memory module</span></span>

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<p>In <a href="Computing" title="Computing">computing</a>, a <b>memory module</b> or <b>RAM stick</b> is a <a href="Printed_circuit_board" title="Printed circuit board">printed circuit board</a> on which <a href="Computer_memory" title="Computer memory">memory</a> <a href="Integrated_circuit" title="Integrated circuit">integrated circuits</a> are mounted.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>

</p><p>Memory modules permit easy installation and replacement in electronic systems, especially computers such as <a href="Personal_computer" title="Personal computer">personal computers</a>, <a href="Workstation" title="Workstation">workstations</a>, and <a href="Server_(computing)" title="Server (computing)">servers</a>. The first memory modules were proprietary designs that were specific to a model of computer from a specific manufacturer. Later, memory modules were standardized by organizations such as <a href="JEDEC" title="JEDEC">JEDEC</a> and could be used in any system designed to use them.

</p><p>Distinguishing characteristics of computer memory modules include <a href="Voltage" title="Voltage">voltage</a>, capacity, speed (i.e., <a href="Bit_rate" title="Bit rate">bit rate</a>), and <a href="Computer_form_factor" class="mw-redirect" title="Computer form factor">form factor</a>.

</p>

<div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2></div>

<p>Types of memory module include:

</p>

<ul><li><a href="TransFlash_Memory_Module" class="mw-redirect" title="TransFlash Memory Module">TransFlash Memory Module</a></li>

<li><a href="SIMM" title="SIMM">SIMM</a>, a single in-line memory module</li>

<li><a href="DIMM" title="DIMM">DIMM</a>, dual in-line memory module

<ul><li><a href="Rambus" title="Rambus">Rambus</a> memory modules are a subset of DIMMs, but are normally referred to as RIMMs</li>

<li><a href="SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMM</a>, small outline DIMM, a smaller version of the DIMM, used in laptops</li></ul></li>

<li><a href="CAMM_(memory_module)" title="CAMM (memory module)">Compression Attached Memory Module</a>, thinner than SO-DIMM</li></ul>

<p>The large memories found in personal computers, workstations, and non-handheld game-consoles normally consist of <a href="Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic RAM</a> (DRAM). Other parts of the computer, such as <a href="Cache_memory" class="mw-redirect" title="Cache memory">cache memories</a> normally use <a href="Static_RAM" class="mw-redirect" title="Static RAM">static RAM</a>. Small amounts of SRAM are sometimes used in the same package as DRAM.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> However, since SRAM has high leakage power and low density, <a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">die-stacked</a> DRAM has recently been used for designing multi-megabyte sized processor caches.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>

</p><p>Physically, most DRAM is <a href="Integrated_circuit_packaging" title="Integrated circuit packaging">packaged</a> in black <a href="Epoxy" title="Epoxy">epoxy resin</a>.

</p>

<div class="mw-heading mw-heading2"><h2 id="General_DRAM_formats">General DRAM formats</h2></div>

<p>Dynamic random access memory is produced as <a href="Integrated_circuit" title="Integrated circuit">integrated circuits</a> (ICs) <a href="Adhesive" title="Adhesive">bonded</a> and mounted into plastic packages with metal pins for connection to control signals and buses. In early use individual DRAM ICs were usually either installed directly to the <a href="Motherboard" title="Motherboard">motherboard</a> or on <a href="Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a> expansion cards; later they were assembled into multi-chip plug-in modules (DIMMs, SIMMs, etc.). Some standard module types are:

</p>

<ul><li><b>DRAM chip (Integrated Circuit or IC)</b>

<ul><li>Dual in-line Package (<a href="Dual_in-line_package" title="Dual in-line package">DIP</a>/DIL)</li>

<li>Zig-zag in-line package (<a href="Zig-zag_in-line_package" title="Zig-zag in-line package">ZIP</a>)</li></ul></li>

<li><b>DRAM (memory) modules</b>

<ul><li>Single In-line Pin Package (<a href="SIPP_memory" title="SIPP memory">SIPP</a>)</li>

<li>Single In-line Memory Module (<a href="SIMM" title="SIMM">SIMM</a>)</li>

<li>Dual In-line Memory Module (<a href="DIMM" title="DIMM">DIMM</a>)</li>

<li>Rambus In-line Memory Module (<a href="RDRAM" title="RDRAM">RIMM</a>), technically <a href="DIMM" title="DIMM">DIMMs</a> but called RIMMs due to their proprietary slot.</li>

<li>Small outline DIMM (<a href="SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMM</a>), about half the size of regular DIMMs, are mostly used in notebooks, small footprint PCs (such as <a href="Mini-ITX" title="Mini-ITX">Mini-ITX</a> motherboards), upgradable office printers and networking hardware like routers.</li>

<li>Small outline RIMM (SO-RIMM). Smaller version of the RIMM, used in laptops. Technically SO-DIMMs but called SO-RIMMs due to their proprietary slot.</li>

<li>Compression Attached Memory Module (<a href="CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a>), a standard developed by <a href="Dell" title="Dell">Dell</a>, which uses a land grid array instead of the more common edge connector.</li></ul></li>

<li><b>Stacked vis-à-vis non-stacked RAM modules</b>

<ul><li>Stacked RAM modules contain two or more RAM chips stacked on top of each other. This allows large modules to be manufactured using cheaper low density wafers. Stacked chip modules draw more power, and tend to run hotter than non-stacked modules. Stacked modules can be packaged using the older <a href="Thin_small-outline_package" class="mw-redirect" title="Thin small-outline package">TSOP</a> or the newer <a href="Ball_grid_array" title="Ball grid array">BGA</a> style IC chips. Silicon dies connected with older <a href="Wire_bonding" title="Wire bonding">wire bonding</a> or newer TSV.</li>

<li>Several proposed stacked RAM approaches exist, with TSV and much wider interfaces, including Wide I/O, Wide I/O 2, <a href="Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> and <a href="High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a>.</li></ul></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Common_DRAM_modules">Common DRAM modules</h2></div>

<p>Common DRAM packages as illustrated to the right, from top to bottom (last three types are not present in the group picture, and the last type is available in a separate picture), this list is in roughly chronological order:

</p>

<ul><li>DIP 16-pin (DRAM chip, usually pre-<a href="Dynamic_random-access_memory#Page_mode_DRAM" title="Dynamic random-access memory">fast page mode DRAM</a> (FPRAM))</li>

<li>SIPP 30-pin (usually FPRAM)</li>

<li>SIMM 30-pin (usually FPRAM)</li>

<li>SIMM 72-pin (often <a href="#Extended_data_out_DRAM_(EDO_DRAM)">extended data out DRAM</a> (EDO DRAM) but FPRAM is not uncommon)</li>

<li><a href="DIMM" title="DIMM">DIMM</a> 168-pin (most <a href="SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> but some were <a href="#Extended_data_out_DRAM_(EDO_DRAM)">extended data out DRAM</a> (EDO DRAM))</li>

<li>DIMM 184-pin (<a href="DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>)</li>

<li>RIMM 184-pin (<a href="RDRAM" title="RDRAM">RDRAM</a>)</li>

<li>DIMM 240-pin (<a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a> and <a href="DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a>)</li>

<li>DIMM 288-pin (<a href="DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a> and <a href="DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a>)</li></ul>

<p>Common SO-DIMM DRAM modules:

</p>

<li>144-pin (64-bit) used for SO-DIMM <a href="SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a></li>

<li>200-pin (72-bit) used for SO-DIMM <a href="DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> and SO-DIMM <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a></li>

<li>204-pin (64-bit) used for SO-DIMM <a href="DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a></li>

<li>260-pin used for SO-DIMM <a href="DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a></li>

<li>262-pin used for SO-DIMM <a href="DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">Bruce Jacob, Spencer W. Ng, David T. Wang (2008). <i>Memory Systems: Cache, DRAM, Disk</i>. Morgan Kaufmann Publishers. pp. 417–418.</span>

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</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20081224070955/http://findarticles.com/p/articles/mi_m0EIN/is_1998_July_21/ai_50179297">"Mitsubishi's 3D-RAM And Cache DRAM incorporate high performance, on-board SRAM cache"</a>. Business Wire. 21 July 1998. Archived from <a rel="nofollow" class="external text" href="http://findarticles.com/p/articles/mi_m0EIN/is_1998_July_21/ai_50179297">the original</a> on 24 December 2008.</cite></span>

</li>

<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text">S. Mittal et al., "<a rel="nofollow" class="external text" href="https://www.researchgate.net/publication/280577113_A_Survey_Of_Techniques_for_Architecting_DRAM_Caches">A Survey Of Techniques for Architecting DRAM Caches</a>", IEEE TPDS, 2015</span>

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</style><div id="Dynamic_random-access_memory_(DRAM)148" style="font-size:114%;margin:0 4em"><a href="Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li>

<li><a href="DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>

<li><a href="LPDDR" title="LPDDR">LPDDR</a> (Mobile DDR)</li>

<li><a href="Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li>

<li><a href="EDRAM" title="EDRAM">eDRAM</a></li>

<li><a href="RLDRAM" title="RLDRAM">RLDRAM</a></li>

<li><a href="Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li>

<li><a href="SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="RDRAM" title="RDRAM">RDRAM</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="UniDIMM" title="UniDIMM">UniDIMM</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Random-access_memory#DRAM" title="Random-access memory">DRAM timeline</a></li>

<li><a href="Synchronous_dynamic_random-access_memory#Timeline" title="Synchronous dynamic random-access memory">SDRAM timeline</a></li>

<li><a href="List_of_interface_bit_rates#Dynamic_random-access_memory" title="List of interface bit rates">Bandwidth</a></li>

<li><a href="Transistor_count#Memory" title="Transistor count">Transistor count</a></li></ul>

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